1. Field of the Invention
The present invention relates generally to methods of operating semiconductor memory cells and, more particularly, to a method for programming nitride read only memory cells.
2. Description of Related Art
A non-volatile semiconductor memory device is designed to maintain programmed information even in the absence of electrical power. Read only memory (ROM) is a non-volatile memory commonly used in electronic equipment such as microprocessor-based digital electronic equipment and portable electronic devices.
ROM devices typically include multiple memory cell arrays. Each memory cell array may be visualized as including intersecting word lines and bit lines. Each word and bit line (or bit line pair) intersection can correspond to one bit of memory. In mask programmable metal oxide semiconductor (MOS) ROM devices, the presence or absence of an active MOS transistor at word and bit line intersections distinguishes between a stored logic ‘0’ and logic ‘1’.
A programmable read only memory (PROM) is similar to the mask programmable ROM except that a user may store data values (i.e., program the PROM) using a PROM programmer. A PROM device is typically manufactured with fusible links at all word and bit line intersections. This corresponds to having all bits at a particular logic value, typically logic ‘1’. The PROM programmer is used to set desired bits to the opposite logic value, typically by applying a high voltage that vaporizes the fusible links corresponding to the desired bits. A typical PROM device can be programmed only once.
An erasable programmable read only memory (EPROM) is programmable like a PROM, but can also be erased (e.g., to an all logic ‘1’s state) by exposing it to ultraviolet light. A typical EPROM device has a floating gate MOS transistor at word and bit line intersections. Each MOS transistor has two gates: a floating gate and a non-floating or control gate. The floating gate is not electrically connected to any conductor, and is surrounded by a high impedance insulating material. To program the EPROM device, a high voltage is applied to the non-floating gate at each bit location where a logic value (e.g., a logic ‘0’) is to be stored. This causes a breakdown in the insulating material and allows a negative charge to accumulate on the floating gate. When the high voltage is removed, the negative charge remains on the floating gate. During subsequent read operations, the negative charge prevents the MOS transistor from forming a low resistance channel between a drain bit line and a source bit line (i.e., from turning on) when the transistor is selected.
An EPROM integrated circuit is normally housed in a package having a quartz lid, and the EPROM is erased by exposing the EPROM integrated circuit to ultraviolet light passed through the quartz lid. The insulating material surrounding the floating gates becomes slightly conductive when exposed to the ultraviolet light, allowing the accumulated negative charges on the floating gates to dissipate.
A typical electrically erasable programmable read only memory (EEPROM) device is similar to an EPROM device except that individual stored bits may be erased electrically. The floating gates in an EEPROM device are surrounded by a much thinner insulating layer, and accumulated negative charges on the floating gates can be dissipated by applying a voltage having a polarity opposite that of the programming voltage to the non-floating gates.
Localized trapped charge devices may also be employed as non-volatile memory cells and may be referred to as charge trapping memory devices.
Charge trapping memory devices are known that can store multiple bits per cell. According to a typical implementation, charge can be stored in two regions of a nitride layer that forms part of a typical charge trapping memory cell. Further, a multiple-bit charge trapping memory cell may be formed of a single transistor, leading to densities of charge trapping memory arrays that are higher than those achieved by many floating gate memories.
Programming a charge trapping memory device may be complicated by several undesirable effects that conspire to impair an ability to determine a program state of a region of the charge trapping memory device. These undesirable effects, which may include program disturbance and a second bit effect, can effectively reduce a programming window associated with operation of the charge trapping memory device.
A need thus exists in the prior art for a method of programming charge trapping memory cells that mitigates undesirable effects, such as program disturbance and the second bit effect, on the programming of the charge trapping memory devices.